top of page
Available Courses

01

 RTL Design & FPGA Implementation
 

Duration: 25 Weeks

Objective: Build strong fundamentals in HDL and complex digital design

 

 

 

Week-wise Topics:

  • Week 1–2: Digital Design Basic

  • Week 3–7: Verilog HDL

  • Week 8: Advanced Verilog: Pipelining

  • Week 9–11: System Verilog Basics

  • Week 12-15: Industry Based Mini Projects

  • Week 16-19: Industry Based Major Project

  • Week 20-22: FPGA Implementation

  • Week 23 : TCL Scripting (Bonus)

  • Week 24-25: Placement Assistance

course fee rtl

02

Desgin Verification (SV + UVM)
 

Duration: 24 Weeks

Objective: Verification Engineer skills using SV + UVM

​

 

 

Topics:

  • Week 1-4: SystemVerilog for Verification: Classes, Constraints, Coverage

  • Week 5-8: Assertions, Scoreboarding, Testbench Architecture

  • Week 9-12: UVM Intro: Factory, TLM, Config DB

  • Week 13-16: UVM Components: Agent, Env, Sequences

  • Week 17-19: Protocol Verification , Reusability

  • Week 20-23: Final Project: Full UVM Testbench for AXI Master or Custom IP

  • Week 24: TCL Scripting (Bonus)

  • Week 25: Placement Assistance

course fee dv
bottom of page